library IEEE; 
use IEEE.STD_LOGIC_1164.all; 
use IEEE.STD_LOGIC_ARITH.all; 
use IEEE.STD_LOGIC_UNSIGNED.all; 

entity counter is 
Port ( clk_in : in STD_LOGIC; 
	rst : in STD_LOGIC; 
	B : inout STD_LOGIC_VECTOR (3 downto 0):="1111"
); 
end counter; 

architecture Behavioral of counter is 

begin 

    process (clk_in, rst) 
    begin 
		
		if (rst = '1') then B <= "0000"; 
		elsif (B = "0111") then B<= "0000";
		elsif (clk_in'event) 
		then  	B <= B+1;
		end if; 
		
	end process; 
end architecture Behavioral; 
